Large capacity memory systems using high-speed access semiconductor memories have become common in recent years. Particularly in the case of a large-capacity memory system for file transfer through a high-speed giga-bit network, flash memories are mounted as blocks in multiple units in a distributed manner, and file data received serially is dividedly programmed to and read from the units in parallel.
For the purpose of dealing with the occurrence of failure, malfunction and the like in these multiple units, the program/read process is carried out while combined with error detection and error correction processes.
FIG. 6 is a functional block diagram showing a functional configuration for the memory control of a conventional information memory system in which one storage unit includes five memory units. FIG. 2 is a frame structure diagram showing a frame structure of data which is programmed to and stored in the memory units in this information memory system. FIG. 7 is a flowchart for explaining a conventional program/read process procedure.
Referring to FIGS. 6, 2 and 7, descriptions will be provided hereinbelow for the conventional operation procedure for programming and reading data to and from units in parallel.
In FIG. 6, an information memory system MS has a memory control unit MCU and NAND flash memory units MU #1 to #5. The memory units MU #1 to #4 record (store) the same input data, or inputted data blocks into which the data is divided in a specified process procedure as described below, and the memory unit MU #5 stores parity data for detecting and correcting a failure in any one of the memory units MU #1 to #4.
The memory control unit MCU includes: a record/playback controller cx; a network interface (I/F) ni for receiving and transmitting data through a network; a RS encoder re for performing a RS (Reed Solomon) encoding process on the data; a RS decoder rd for performing a RS decoding process on the data; and a unit manager bc for controlling the data received and transmitted through the memory units MU.
The record/playback controller cx performs a RS process on serial data received and transmitted through the network interface ni at high speed, and performs overall control of the program (recording) and read (playback and file output) of the input/output data of the memory units MU through the unit manager bc.
Data received and transmitted through the network is formatted into data packets which are allocated per communication channel, and are treated as a large frame block with a capacity of 20 channels, for example. In addition, since the data which is dividedly recorded in the four memory units MU #1 to #4 is read, the data for five channels is recorded in each memory unit MU.
The unit manager bc controls the operation of the five memory units MU #1 to #5 including the above four memory units MU for RS-processed data and additionally one memory unit MU for storing (recording) parity data. Although the configuration having the five memory units MU including the four data recording memory units MU and the one memory unit MU for parity is described herein as an example, the configuration may include four memory units MU including three data recording memory units MU and one memory unit MU for parity.
The unit manager be includes: a divider dv for dividing the received data into four data blocks for the memory units MU #1 to #4, respectively, and adding header information for identification information, error correction and the like to each data block; a parity section pc for adding check bits for detecting an error to the data; checksum adders cs #1 to #5 for adding checksum bits to the data received from the divider dv and the parity section pc, and transmitting the resultant data to the memory units MU #1 to #5 as program data; buffers BF #1 to #5 for buffering read data received from the memory units MU #1 to #5; an error check processor EC; an integrator RC for integrating the four blocks of data into the original series of RS data; and a CPU ca for managing the program and read of the data depending on whether or not each memory unit MU operates normally, by monitoring the buffers BF and the error check processor EC.
The error check processor EC checks an error in the checksums and the like of the data received from the buffers BF #1 to #5, and checks the parity added by the parity section. When detecting an error from one memory unit MU, the error check processor EC rebuilds the four blocks of data by correctly rebuilding the data read from the memory unit MU having the error by use of the data read from the normal memory units MU other than the memory unit MU having the error.
These components in the unit manager bc are connected to the CPU ca through a bus line, and the unit manager bc is connected to the record/playback controller cx through another bus line; or may additionally function as the record/playback controller cx.
In a flowchart shown in FIG. 7, record data like “abc xyz” (see FIG. 2A) is received from the network (step s1); the RS encoder rs RS-encodes the record data into “rx(abc . . . xyz)” (see FIG. 2B) (step s2); and then, the divider dv divides the encoded data into four blocks with control headers h1 to h4, each inclusive of identification information and the like, added to the respective four blocks (see FIG. 2C).
Further, the parity section pc adds parity data P (see FIG. 2D) to the four divided data blocks. For example, the parity data P is a data block whose frame structure is “h5Prx(a-z)” corresponding to the memory unit MU #5 (step s3). This parity process is achieved by horizontal and vertical parity for the purpose of enabling data rebuild from an error.
A checksum “&” for detecting an error in the data to be programmed to the memory units MU #1 to #5 is added to each of these data blocks (see FIG. 2E) by the checksum adder cs (step s4). For example, “h5Prx(a-z)&” is programmed to the memory unit MU #5 (step s5). In addition, “&” added for the checksum takes different values from one data block to another, but the common symbol “&” is used for the different data blocks for the sake of simplicity.
After programming, the CPU ca waits for an instruction from the record/playback controller cx (No in step s6). Further, upon receipt of a read instruction (Yes in step s6), the CPU ca instructs the memory units MU #1 to #5 to prepare for the read (enter into a read cycle) (step s7).
The memory units MU #1 to #5 output the read data to the buffers BF #1 to #5 in order from the top of the read data (step s8). If the amount of buffered data exceeds a specified minimum unit (Yes in step s9), each of the buffers BF #1 to #5 outputs a read request to the CPU ca (step s10).
If the CPU ca receives the read request from all the five memory units MU (Yes in step s31), the CPU ca immediately starts to perform simultaneous read control for the memory units MU (step s32).
The error check processor EC checks the header information of the read data blocks transmitted (step s33) from the buffers BF, namely, the memory units MU #1 to #5. If there is no error in the header (No in step s34), the error check processor EC performs the sum check and the parity check on the data block read from each memory unit MU, and rebuilds the original data block by correcting errors (step s35), thus transmitting the reconstructed original data block.
The integrator RC integrates these transmitted data blocks into one data block (step s36), and further outputs the one data block to the RS decoder rd. Further, the original series of RS-processed data is decoded by the RS decoder rd (step s37), and is eventually played back (step s38).
On the other hand, if there is an error in the header information of the data from any one of the buffers BF (Yes in step s34), all the transferred blocks are discarded (step s39).
In addition, if the amount of data inputted into any buffer BF (for example, #4) from a faulty memory unit MU does not reach the minimum unit after the faulty memory unit MU starts the preparation for the read (No in step s31), the CPU ca cannot start to perform the read control in a freezing state forever, because the CPU ca continues waiting for all the five read requests to arrive at the CPU ca.
High-speed response is achieved by the conventional method in which data inputted and transmitted at high speed is divided into blocks and the divided data blocks are programmed to and read from the respective flash memories in parallel at high speed. However, the conventional method has a problem that: if a fault occurs in any one of the multiple memory units, not only can the data in the faulty unit not be read, but also the entire data cannot be read: and the freezing state accordingly occurs.
For dealing with the occurrence of disorder of a faulty disc, there has been proposed a method in which a recovery process is carried out by referring to the timer after the error detection (for example, Japanese Patent Application Publication No. Hei 11-95933, contents of which are hereby incorporated by reference).
From the reading side outside of the system, however, the condition until the recovery also looks like the operation halt or freeze.